This invention relates to a semiconductor integrated circuit device and method of fabrication thereof, such as a semiconductor device provided with an electrostatic protective circuit and an internal circuit that are formed on the same semiconductor substrate, with, e.g., a MIS (Metal-Insulator-Semiconductor) element used as the internal circuit. More particularly, the present invention relates to a semiconductor integrated circuit device in which a measure against hot carriers and a measure against electrostatic breakdown are taken, and whose internal circuit has a MOS field effect transistor having two diffusions to form the drain region (e.g., double-diffused structure or LDD (Lightly Doped Drain) structure), as well as a method of manufacturing the same.
Miniaturization of semiconductor devices (ICs) has been attempted to increase their operating speed and improve their integration density. MOS elements (MOSFETs), which are typical examples of MIS elements (MISFETs), are no exception. To miniaturize MOS elements, the thickness of their gate oxide films has been reduced and the length of their channels has become shorter and shorter. This means that a relatively strong electric field is generated within the device, so that the injection of hot carriers into the gate oxide film occurs, and the threshold voltage shifts or a degradation of mutual conductance occurs.
A double-diffused drain structure such as that shown in FIG. 1 has been proposed to solve these problems. FIG. 1 is a section through a typical N-channel MOSFET. Reference numeral 1 denotes a P-type silicon semiconductor substrate, 2 a silicon dioxide (SiO.sub.2) film, 3 a gate oxide film, and 4 a gate electrode. In order to reduce the strong electric field in the proximity of the drain, both drain and source have a double-diffused drain structure consisting of an N.sup.- -type layer 5 of phosphorus (P) and an N.sup.+ -type layer 6 of arsenic (As) (refer to E. Takeda, et al., "An As-P (N+-N) Double Diffused Drain MOSFET for VLSI's", Digest of Technical Papers, Symp. on VLSI Technology, OISO, Japan, pp. 40-41 (Sept. 1982), the contents of which is incorporated herein by reference).
In a semiconductor device, especially a microminiaturized semiconductor device, comprising metal-oxide-semiconductor field effect transistors (MOSFETs), it is proposed to employ the LDD structure for a source and a drain to the end of preventing the appearance of hot carriers. With the LDD structure, source and drain regions are each constructured of a high impurity concentration region formed away from a gate electrode (hereinbelow, expressed as `formed in offset to a gate electrode`), and of a low impurity concentration region disposed between the high impurity concentration region and the gate electrode. Owing to the LDD structure, the electric field of a drain edge in the direction of a channel is relaxed, with the result that the appearance of hot carriers is suppressed. Thus, the degradations of element characteristics attributed to the hot carriers can be restrained, to enhance reliability. In case of, for example, an N-channel MOSFET (hereinbelow, termed `NMOSFET`), the low impurity concentration region mentioned above is set at a concentration on the order of, e g., 10.sup.13 cm.sup.-2 and, e.g., at a length of 0.2-0.4 .mu.m.
The LDD is described in P. J. Tsang et al, IEEE Transactions on Electron Devices, Vol. ED-29, No. 4 (1982), p. 590.
A protective circuit is usually formed on the same semiconductor substrate to protect the MIS element forming the circuit from abnormal signals from outside the IC. As shown in FIG. 12, the protective circuit (e.g., electrostatic protective circuit) is a circuit to prevent the destruction of the gate insulating film of a MISFET 71 of a first stage inverter 68, the gate electrode of which is connected with a bonding pad 8 through a resistor 10. The destruction occurs when electrostatic energy is applied to the bonding pad.
A circuit such as that represented by the equivalent circuit diagram of FIG. 2 has been known as a typical protective circuit 9 used for protecting circuits other than the protective circuit, that is, the internal circuit of the IC. A signal to the internal circuit is applied to a bonding pad 8 through a diffusion resistor 10 of which one end is connected to the pad 8, and a clamping MOSFET 11 whose gate and source are grounded is connected to the junction between the resistor 10 and the internal circuit.